The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
In the past the die and package were first attached and then the electrical connections from the die to the package were made by wire bonding. The wire bonding procedure is simple in concept. A thin (0.7 to 1.0 mil) wire is first bonded to the chip bonding pad and spanned to the inner lead of the package lead frame. The third action was to bond the wire to the inner lead. Lastly, the wire is clipped and the entire process repeated at the next bonding pad. While simple in concept and procedure, wire bonding was critical because of the precise wire placement and electrical contact requirements. In addition to accurate placement, each and every wire must make a good electrical contact at both ends, span between the pad and the inner lead in a prescribed loop without kinks, and be at a safe distance from neighboring lead wires. Wire loops in these packages are 8 to 12 mils, while those of ultrathin packages are 4 to 5 mils. Wire bonding has been done with either gold or aluminum wires. Both types of wire are highly conductive and ductile enough to withstand deformation during the bonding steps and remain strong and reliable.
Wire bonding between a die and a package has several problems. One problem is that a wire bond attachment to a die limits the number of pads and placement of the pads on the die. In addition, minimum height limits are imposed by the required wire loops. Another problem is that there is a chance of electrical performance problems or shorting if the wires come too close to each other. The wire bonds also require two bonds and must be placed one-by-one and there are resistances associated with each bond. The wires are also relatively long and thus could contribute significantly to lead inductance and capacitance. This could limit acceptable signal speed in the system.
To increase the number of pad sites available for a die and to address the problems stated above and other problems, a different chip packaging technique called controlled collapse chip connection or flip chip packaging is being adopted. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump connects to a corresponding package inner lead. The packages which result are lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. These packages are occasionally referred to as "Ball Grid Array" (BGA). Alternatively, the output terminals of the package may be pins and such a package is commonly known as pin grid array (PGA) package.
Alternatively, the output terminals of the package may be pins and such a package is commonly known as pin grid array (PGA) package.
Once the die is attached to the package the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer of which the die is singulated from. The side of the die including the epitaxial layer containing the transistors, and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon. The positioning of the circuit side provides many of the advantages of the flip chip. However, in some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. When a circuit fails or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is obtained only from the backside of the chip. This is challenging since the transistors are in a very thin layer (about 10 .mu.m) of silicon buried under the bulk silicon (&gt;500 .mu.m). Thus, the circuit side of the flip chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Although the circuit of the integrated circuit (IC) is buried under the bulk silicon, infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using IR microscopy. On a die that is 725 microns thick, this means removing at least 625 microns of silicon before IR microscopy can be used. Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished in two or three steps. First, the die is thinned across the whole die surface. This is also referred to as global thinning. Global thinning is done to allow viewing of the active circuit from the backside of the die using IR microscopy. Mechanical polishing is one method for global thinning.
Once an area is identified using IR microscopy as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques are used to thin an area smaller than the die size. Laser microchemical etching of silicon is one method of local thinning. One method for laser microchemical etching of silicon is accomplished by focussing a laser beam on the backside of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone. This is a silicon removal process used on the 9850 SiliconEtcher.TM. tool by Revise, Inc. (Burlington, Mass). This laser process is suitable for both local and global thinning by scanning the laser over a part or whole surface of the die.
Sometimes it is necessary for failure analysis, or for design debug, to make electrical contact and probe certain nodes in the circuit that is on the circuit side or front side of the die. This is generally done by milling through the die to access the node, or milling to the node and subsequently depositing a metal to electrically access the node. These access holes need to have high aspect rations. For design debug, it is desirable to have the capability of cutting the interconnect lines and rerouting of the interconnect lines. Milling through silicon with fairly high aspect ratio trenches is slow and is almost impractical for silicon thickness greater than 10 microns. For these reasons, it is necessary to have a method and apparatus which will provide for controlled thinning flip chip bonded IC devices to less than 10 micron thickness. It is also necessary to have a method where the thickness of the silicon can be determined with sufficient accuracy to avoid milling off the node to which access is being sought. Milling off the node could often jeopardize further device analysis.
The need for a method for accurately determining the thickness of the silicon is not eliminated by an approach where the backside is thinned to a distance away from the package to which the die is attached. Various parts tolerances do not allow for such a simple solution to approaching the circuit side of the die from the back side of the die. One tolerance issue revolves around keeping the height of solder ball contacts on the die substantially uniform for every packaged device of a particular type. Even though the solder ball contacts have a tolerance requirement, when the solder is reflowed to attach the die to a package, the amount of change in height due to solder reflow can vary by several microns. The thickness of the die between the circuit side and backside is also subject to tolerance differences. Since the thickness of the starting silicon wafer is a non-essential parameter for making a functioning die, typically the die thickness is not known to an accurate level. For instance, a typical die for a microprocessor may have a die thickness of 725.+-.15 microns. The end result is tolerance stacking due to the tolerances for the size of the solder balls, the height at which the die is attached and the thickness of the die. These tolerances stack up such that there can be tens of microns of difference in height from the top surface of the package to the top surface of the die among different packaged devices. Although this does not sound like much of a tolerance problem, it should be noted that the epitaxial layer is only between 2 and 10 microns thick. As a result, the thickness of the remaining silicon of a trench cannot be gauged by measuring from the top surface of the package to the bottom of the trench. Stack up of the tolerances of the various parts precludes simply "measuring up" from the package to which the die is attached to determine where the epitaxial layer containing the transistors begins. Simply put, such an approach is not accurate enough to prevent ruining the circuitry or transistors that must be analyzed or debugged. Once the circuitry or transistors are ruined, analysis or debugging is impossible.
Therefore, the introduction of flip chip technology requires a method and apparatus for determining the thickness of silicon between a portion of the active circuitry near the circuit side of the die and the backside of the die. This is necessary to eliminate any guesswork as to the location of the circuitry while the backside of a die is being removed. If this guesswork is eliminated, it facilitates failure analysis and debugging of the circuitry associated with a particular integrated circuit. Furthermore, when the position of the circuitry is known or can be determined from the backside removal of the silicon, getting to the circuitry can be accomplished in less amount of time. Therefore, to facilitate more effective and efficient backside thinning processes, a measurement method and apparatus sensitive to the thickness of the remaining silicon is needed. Such a method and apparatus would be useful and essential for controlled backside thinning of silicon.